1. Field of the Invention
The present invention relates to receiver and level converter circuits, and chips and systems employing such circuits. More particularly, the invention relates to a circuit for use in receiving a low-level signal, such as from a logic or memory circuit and converting such signal to a higher-level signal for output to another circuit.
2. Background and Description of the Related Art
The need for either a receiver circuit, or a level converter circuit, or both, may arise in several situations. One situation is where integrated circuit chips are physically separated by some distance, and signals traveling between them become attenuated because of line resistance, interference or other factors. It thus becomes necessary to include a receiver on one or both chips to restore the signal to its former level (i.e., provide high gain), in order to permit further processing to proceed.
Another situation, which requires a combined receiver and level converter device, arises when chips employing different technologies need to be interconnected. Logic and memory circuits, for example, may employ any of several technologies, including ECL (emitter-coupled logic), TTL (transistor-transistor logic), FET or CMOS (complementary metal-oxide semiconductor) and BICMOS (combined bipolar and CMOS transistors). Each technology normally operates with signals of different voltage levels, and different voltage swings between the "high" and "low" levels. A typical ECL signal may, for example, show a relatively small swing, such as 0.8 V or less. By contrast, a CMOS signal may show a larger swing of about 5.0 V. Because of this difference, interconnecting two circuits of different technologies thus normally requires at least one, and more often two, level converter circuits.
Regardless of the particular environment in which the receiver circuit is used, it is desirable to provide a circuit that not only provides high gain, but also is relatively immune to noise at the input (i.e., has high noise margin). "Noise" in this context could mean either random fluctuations in the input signals due, for example, to power supply or temperature variations, or it could mean differences in circuit device parameters due to variations in the processing of the semiconductor devices. Ideally, the receiver circuit should be able to tolerate all types of noise.
Various signal receiver and level converter circuits are known in the art. One example of a logic level conversion circuit which converts ECL logic levels to CMOS logic levels is that shown in U.S. Pat. No. 4,779,016. Here, a bipolar differential amplifier is coupled to a configuration of field effect transistors to accomplish the configuration of field effect transistors is shown in U.S. Pat. No. 4,453,095.
In another arrangement, U.S. Pat. No. 4,438,349 shows a CMOS differential amplifier for converting signals from one level to another. U.S. Pat. No. 3,988,595 and 4,782,251 also show circuits for converting signal levels.
The above prior art circuits, however, have a disadvantage in that either no feedback is provided between the output and the input of the differential amplifier, or only limited feedback is provided through one feedback loop. This limited feedback arrangement allows for noise at the input to have a relatively large effect on the signal at the output. The overall gain of the circuits also appears to be quite limited.
One way of increasing the gain as well as the noise margin for a difference amplifier receiver circuit is to introduce sufficient feedback to provide an output signal showing wide hysteresis in response to the input signal. Although hysteresis circuits have been developed, they have not typically utilized two feedback loops or have been employed in the context of a receiver or level converter circuit, particularly in an environment where a small level signal (such as ECL) must be converted to a larger level signal (such as CMOS or BICMOS), or where improved noise margin is desired.